Dimmer Circuit with Improved Inductive Load Imbalance Protection

ABSTRACT

A protection circuit for protecting a dimmer circuit controlling an inductive load including an imbalance detector for detecting an asymmetrical operation in the load and circuit control means for causing the dimmer circuit to reduce a DC component in the load upon detection of the asymmetrical operation. A load imbalance detector is also disclosed having a load DC component detector, a comparator and a signal generating means for generating a circuit shut down signal if the DC component exceeds a pre-set DC threshold.

TECHNICAL FIELD

This invention relates to circuit arrangements for controlling the powerprovided to a load and in particular, to dimmer circuits forcontrolling, for example, the luminosity of a light or the speed of afan.

BACKGROUND TO THE INVENTION

Dimmer circuits are used to control the power provided to a load such asa light or electric motor from a power source such as mains. Suchcircuits often use a technique referred to as phase controlled dimming.This allows power provided to the load to be controlled by varying theamount of time that a switch connecting the load to the power source isconducting during a given cycle.

For example, if voltage provided by the power source can be representedby a sine wave, then maximum power is provided to the load if the switchconnecting the load to the power source is on at all times. In this waythe, the total energy of the power source is transferred to the load. Ifthe switch is turned off for a portion of each cycle (both positive andnegative), then a proportional amount of the sine wave is effectivelyisolated from the load, thus reducing the average energy provided to theload. For example, if the switch is turned on and off half way througheach cycle, then only half of the power will be transferred to the load.Because these types of circuits are often used with resistive loads andnot inductive loads, the effect of repeatedly switching on and off powerwill not be noticeable as the resistive load has an inherent inertia toit. The overall effect will be, for example in the case of a light, asmooth dimming action resulting in the control of the luminosity of thelight. This technique will be well understood by the person skilled inthe art.

A power semiconductor in the form of a triac is typically the principalload controlling device in phase control dimming applications. Such adevice offers advantages of relatively low conduction losses and highrobustness, but has the disadvantage of operating sensitivity to loadtype.

When controlling magnetically saturable inductive load types includingelectric fan motors and particularly iron core transformer based lowvoltage lighting, asymmetrical dimmer conduction may result. With theseload types triac latching into the conducting state may occur only inone half cycle polarity due to the presence of magnetic asymmetry in theload. Once this condition has commenced, it is generally sustained asthe asymmetric load impedance condition becomes exacerbated. A severereduction in load inductance for one half cycle polarity results in acorresponding high level DC current component. This can rapidly lead tooverheating of primary windings of the transformer.

Generally, dimmer units specified for use with inductive loads requirethe use of very sensitive triacs so that the likelihood of asymmetricaloperation is reduced. Sensitive triacs axe comparatively less robust andtherefore not as suitable for universal dimming applications.

It is therefore an object of the present invention to provide analternative method and apparatus for addressing load imbalanceconditions

SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provideda protection circuit for protecting a dimmer circuit controlling aninductive load, the protection circuits including: an imbalance detectorfor detecting an asymmetrical operation in the load; and circuitshut-off means for causing the dimmer circuit to stop operating upondetection of the asymmetrical operation.

According to a second aspect of the present invention, there is provideda load imbalance detector for use in a dimmer circuit controlling aninductive load, including: a load DC component detector to detect a DCcomponent in the load; a comparator for comparing a magnitude of the DCcomponent detected by the load DC component detector with a referencevoltage; and a signal generating means for generating a circuitshut-down signal if the DC component exceeds a pre-set DC voltagethreshold above the referenced voltage.

Preferably, the load DC component detector detects a DC sub-component ina positive cycle and detects a DC sub-component in a negative cycle andwherein said magnitude of the DC component is the difference between therespective DC sub-components.

Preferably, the load DC component detector includes a first resistordivider chain for detecting said DC sub-component in the positive cycleand a second resistor divider chain for detecting said DC sub-componentin the negative cycle and wherein a divider junction of the first chainis connected to a first side of a capacitor and a divider junction ofthe second chain is connected to a second side of the capacitor, avoltage across which provides said magnitude of the DC component.

Preferably, the comparator includes a first pnp transistor having itsbase connected to said first side of said capacitor and its emitterconnected to said second side of said capacitor and a second pnptransistor having its base connected to said second side of saidcapacitor and its emitter connected to said first side of said capacitorand each respective collector connected to an input of said signalgenerating means.

Alternatively, the imbalance detector detects a difference between theconduction period of consecutive positive and negative half cycles.Preferably, the imbalance detector will register a load imbalance if thedifference between the consecutive positive and negative half cyclesexceeds a preset threshold.

Preferably, the circuit control means causes the dimmer circuit to shutdown.

Optionally, the circuit control means causes the dimmer circuit toreduce a conduction angle of the dimmer circuit to a point where the DCcomponent reduces to below a preset threshold.

The invention therefore eliminates the need for traditional methods ofattempting to reduce the likelihood of load imbalance using expensivecomponents.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a first embodiment of the dimmer circuit of the presentinvention;

FIG. 2 shows an alternative arrangement of the triac control circuitportion of FIG. 1;

FIG. 3 shows a current switch control circuit which may be used as analternative to the voltage switch control circuit of FIGS. 1 and 2;

FIG. 4 shows a simplified block diagram of the circuit of FIG. 1; and

FIG. 5 shows art alternative arrangement for the impedance loadimbalance detector portion of FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A preferred circuit design of a 2-wire, leading edge phase control lightdimmer/fan speed controller is shown in FIG. 1. The design shown in FIG.1 is particularly effective in that it is electromagnetic compatible(EMI compliant). This refers to the amount of electromagneticinterference (EKE) that is generated by the circuit. The amount ofradiation generated by dimming circuits due to the high frequencyswitching of the circuit is heavily regulated and such circuits must notexceed the regulated level of EMI.

The circuit design of FIG. 1 controls the level of EMI generated by thecircuit via active control of the rate of rise of load voltage at eachmain half cycle. A power semiconductor in the form of an IGBT is usedfor this function. The IGBT and associated drive control circuitry isconnected to the DC side of a diode bridge to allow control ofpolarities of mains voltage.

A power triac is used to handle the load current once the IGBT hasperformed the required slow switching function. This reduces powerdissipation to a minimum since it has an on-state voltage lower thanthat of the IGBT/bridge conduction voltage.

The IGBT circuit of FIG. 1 can be separated into the following blocks:

-   -   low voltage DC power rail    -   main voltage zero cross detector    -   power up drive inhibit    -   control timing    -   IGBT gate drive

Power for the IGBT control circuit is derived from mains via the load,in each half cycle during the time period before IGBT operationcommences, ie. while mains voltage appears across the dimmer. Overallcurrent consumption is long enough to allow the use of a relatively lowdissipation resistive chain provided by R1, R2, R4 and R5. A smoothingcapacitor, C9 stores enough charge provided at the start of each halfcycle to provide circuit current for the remaining period, withrelatively low ripple voltage. Excess supply current is shunted byvoltage regulating zener diode DZ1 with the resultant of nominal DCpower rail of 15 volts. This arrangement provides the low voltage DCpower rail block referred to above.

The mains voltage zero cross detector resets the control timing circuit(described in more detail below) in each half cycle after load currentcommences. Tuning is allowed to start again when mains voltage reappearsacross the circuit in the following half cycle. For resistive loads thiswill correspond to mains voltage zero crossing. For inductive loadshowever, this corresponds to load current zero crossing, which occurslater than mains voltage zero crossing.

Transistor Q2 with its emitter connected to the DC rail, has its basedriven by the power supply voltage dropping resistor chain describedabove. The collector pulls “sync” high whenever the voltage across thedimmer circuit is below the DC rail voltage. Conversely, when mainsvoltage exists across the dimmer circuit, transistor Q2 base emitterjunction is reverse biased, preventing the collector from pulling up.During this time supply current is delivered to the DC rail viabase-emitter shunting diode D4.

Reset of the controlled timing capacitor C7 is performed by dischargetransistor Q12, which is driven by limiting resistor R21 from “sync”output of Q2. Transistor Q12 has base-emitter bypassed resistor R22 andcapacitor C6 to reduce off-state leakage and to enhance EFT immunity.

The function of the power-up drive inhibit block is to inhibit theoperation of the dimmer circuit for the first few main half cycles atpower-up by temporarily by-passing the control timing capacitor C7charging current. This is required to enable correct operation of thesoft-start mechanism, which relies on an established DC voltagereference to function. A small capacitor C1, effectively connected tothe DC rail, provides a current via diode D3 to drive dischargetransistor Q12 during the period while the rail is rising at power-up.Blocking diode D3 isolates C1 from Q12 drive circuit once C1 has becomecompletely charged after the power-up event. Resistor R8 thereafterserves to hold C1 in the fully charged state, in addition to providing adischarge path at power off.

The control timing block is used to provide the dimmer circuit withimmunity to mains voltage ripple injection.

At the start of each mains half cycle, timing capacitor C7 charges viamains/load through current limiting resistors R6 and R7. A referencevoltage determined by zener diode DZ4, sourced by resistor R39, is usedas a charge threshold level for terminating the timing process. Thevoltage on the positive side of C7 must always reach a level ofapproximately two diode drops above this reference level, as determinedby series connected diode D5 and transistor Q4, in order to initiateIGBT operation. At the pre-defined threshold voltage, the timingcapacitor charging current is diverted to transistor Q4 in order tooperate the IGBT drive control stage.

Adjustment of control firing angle is facilitated by a variable controlvoltage source connecting to the negative side of the timing capacitor.This control voltage is derived from zener diode DZ4 referenced voltageusing main dimmer control potentiometer VR1. An RC filter made up of R28and C13 provides a soft-start feature at power up due to the zeroinitial capacitor voltage condition. Buffering of the filtered controlvoltage is performed by cascaded transistors Q3 and Q15 to provide a lowimpedance source voltage. Resistor R36 bypasses the base-emitter oftransistor Q15 to reduce leakage effects.

At the maximum control voltage (for maximum dimmer conduction angle),the required timing capacitor charging voltage is at its lowest. Theminimum required timing capacitor charging voltage is equal to oneforward voltage diode drop, as determined by diode D5, in addition toesmall voltage across resistor R11. This level is independent of theabsolute value of the zener diode DZ4 reference voltage. Consequently,the maximum conduction angle is inherently limited, being largelyindependent of component parameters, thus ensuring sufficient current isalways available to supply the DC rail. Resistor R11 is included tofurther restrict the maximum dimmer conduction angle.

PTC1 is placed in series (on the reference voltage side) with VR1 toprovide automatic reduction of conduction angle in the event of dimmerover-temperature due to over loading of the product. Trimpot VR2 isplaced in series (circuit common side) with VR1 to allow adjustment ofthe minimum conduction angle, by raising the minimum control voltage.

The IGBT gate drive control circuit is provided by transistors Q16, Q17and Q5. The circuit behaves as a non-retriggerable monostable andprovides controlled gate drive current to the IGBT to achieve thedesired slow switching outcome. Transistor Q5, connected to the DC rail,acts as a switch to source IGBT gate current via timing resistor R38 atturn on. Transistor Q17, connected to circuit common, acts as a switchfor rapid discharge of IGBT gate charge at turn off.

Base drive current for input transistor Q16 is sourced by Q4 from thecontrol timing circuit. The base-emitter is bypassed by resistor R27 andcapacitor C4 to reduce off-state leakage and to enhance EFT immunity.When transistor Q16 is mot driven, transistor Q17 is sufficiently biasedvia resistors R3, R13, R35 and R48, so that the collector holds the IGBTgate in the discharged (off) state. In this condition, transistor Q5 isnot sufficiently biased to operate. When transistor Q16 is driven,resistor R35 provides sufficient bias to operate transistor Q5, whichprovides temporary regenerative base drive for transistor Q16 via RCnetwork R37 and C8. This result in monostable action (approximately 300micro seconds output duration). During this active condition, bias isremoved from transistor Q17.

The combination of IGBT series gate current limiting resistor R38 andparallel gate capacitor gate C14 provides the required slow turn-oncharacteristic for EMC control at IGBT turn on. The values selected arespecifically suited to the IGBT used, in this case IRG4 BC20S.

The triac control circuit is shown in FIG. 1 in the circuit block on theAC side of the diode bridge. The primary function of this circuit is totrigger the triac Q23 once the IGBT has completed the slow-switching EMCemission reduction operation, on a per half-cycle basis. An essentiallysymmetrical circuit is used to provide a triac gate drive pulse inquadrants 1 and 3 (gate drive polarity follows mains polarity).

Additional functions performed by the triac control circuit includeover-current protection and dimmer over-voltage protection. Either ofthese conditions result in immediate iliac triggering. Duringover-current conditions (for example incandescent inrush current), thetriac shunts current away from the IGBT. During over-voltage conditions(for example mains transients), the triac shunting action transfers thetransient potential to the load.

The triac control circuit derives its power, from the mains via theload, in each half cycle during the time period before IGBT operationcommences, that is while mains voltage appears across the dimmer.Average current consumption is long enough to allow the use of arelatively low dissipation resistive chain made up of R16, R17, R18 andR19. During each mains half-cycle, current provided by the resistorchain is used to charge the capacitor C10 to a voltage with polaritydetermined by the mains. The voltage developed across capacitor C10 islimited to approximately 20 volts for each polarity, as defined byshunting zener diodes DZ2 and DZ3. The sequence of operation of thedrive circuit for each half cycle polarity is as follows:

-   -   reservoir capacitor C10 is charged while mains voltage is        present.    -   A 100 micro second time delay circuit (R24 and C3) is initiated        after the dimmer voltage falls below approximately 20 volts due        to IGBT operation;    -   At the end of the time delay, the triac Q23 gate is supplied        with current from capacitor C10 via limiting resistor R41.

In the positive mains half cycle, reservoir capacitor C10 is charged toapproximately 20 volts from mains through limiting resistors R16, R17,R18 and R19 via the base-emitter junction of transistor Q18. When dimmerterminal voltage drops below the 20 volts at threshold, transistor Q6provides charging current via current limiting resistor R24 fortime-delay capacitor C3. When the voltage across capacitor C3 reachesapproximately 0.6 volts, transistor Q13 operates, which in turn providesbasic current drive for output transistor Q1 via current limitingresistor R10. Some regenerative feedback from the collector oftransistor Q1 to the base of transistor Q13 via resistor R12 speeds upthe switching action. The collector of transistor Q1 drives, the triacgate via steering diode D7A and gate current limiting resistor R41. Thefunction of diode D7A is to isolate the triac gate circuit duringcharging of reservoir capacitor C10 during the negative half mains halfcycle. This is necessary because the base-collector junction of outputtransistor Q1 is forward biased in this period.

Capacitor C3 has the additional role of enhancing EFT immunity fortransistor Q13, while resistor R26 reduces transistor leakage.Similarly, resistor R9 reduces leakage of output transistor Q1 whichwould consequently affect the C3 timing period.

The operation of the circuit for the negative mains half cycle is thesame as described above but uses the mirrored set of components.

Applications utilising isolated PWM control for dimming level requirethat both the IGBT (Q22) and iliac (Q23) together with associated drivecircuitry is permanently connected to mains. This differs from themanually controlled two-wire modular dimmer application where a seriesmains interrupting switch is always used for load on/off control.

Generally in the dimmer circuit design, triac firing operation commencesas the dimmer terminal voltage falls below a threshold level as aconsequence of IGBT operation.

A modification to this method of operation is required for the isolatedcontrol interface dimmer which has permanent mains connection. In thiscase it is necessary to disable triac triggering which would otherwisebe initiated near the end of every mains half cycle. Although the loadis effectively in the off state, due to the very low prevailing triacconduction angle and hence load voltage, the resulting line conductedEMC emission levels would be quite large due to such triac operation.

To address this situation, additional circuitry has been incorporatedwhich differentiates between the rate of change of mains voltage due toIGBT operation during dimming, and that due to normal mains voltagewaveform when the MST is not activated via the isolated controlinterface.

In dimming operation, the triac drive circuit is normally disabled andis only enabled for a short period after detection of the relativelyfast rate of change of load terminal voltage due to ICU operation.During load off state conditions, the triac drive circuit is not enabledby the relatively slow rate of fall of mains voltage near the end ofeach half cycle.

Some important design considerations for this additional circuitry arethat a high immunity to mains transients and mains ripple controlsignals is maintained.

FIG. 2 shows a modified circuit of the triac control circuit of FIG. 1as described above, in which common elements are identified accordingly.

A description of circuit operation with reference to FIG. 2 for onemains half-cycle polarity follows.

A clamping transistor, Q300 is used to disable the triac drive circuitfrom operating by shunting the charging current for the triac firingtime delay capacitor, C3. A filter capacitor, C300 is normally chargedfrom the ±20V rail via resistive divider elements, R300 & R301 with suchpolarity as to maintain the bias to the clamping transistor.

During IGBT, Q22 operation, the resulting bridge voltage dv/dt producessufficient current through a small mains coupling capacitor, C301 torapidly discharge the filter capacitor in order to reverse bias theclamping transistor base-emitter junction. The clamping transistorremains biased off long enough to allow normal charging of the triacfiring time delay capacitor, due to the filter capacitor/bias resistorstime constant.

Immunity to mains ripple injection is achieved through thelow-pass-filter action of the capacitor and bias resistors.

Without IGBT operation the relatively low dv/dt associated with themains voltage waveform is insufficient to remove the bias voltage on thefilter capacitor. Thus the clamping transistor continues to bypasscharging of the triac firing delay capacitor, preventing possibility oftriac operation.

A series resistor element, R302 for the mains coupling capacitorprovides current limiting protection under mains surge/transientconditions.

A reverse connected diode, D300A is required across thecollector-emitter junction of the clamping transistor, Q300 in order toprevent the transistor from interfering with correct operation of theassociated transistor, Q301 in the opposite half cycle. In opposite halfcycle, the collector-base junction of Q300 becomes forward biased andcan source sufficient bias current to operate the associated transistor,Q301. The parallel diode, D300A works by limiting the collector voltageto only one forward diode drop, therefore limiting base drive voltagefor associated transistor, Q301 to approx. zero volts.

The above voltage driven triac control circuit may equally be replacedby a current driven triac control circuit as shown in FIG. 3. Onceagain, the primary function of this circuit is to trigger the triac oncethe IGBT his completed the slow-switching EMC emission reductionoperation, on a per half-cycle basis. The circuit is essentiallysymmetrical and is used to provide a triac gate drive pulse in quadrants1 and 3 (gate drive polarity follows mains polarity).

In operation, a current sense resistor, R32, is used to derive drivepotential for the entire triac drive circuit. After a defined loadcurrent threshold is achieved, sufficient for triac gate requirements,excess current is by-passed by series connecting diodes D3 and D4. Thedeveloped sense voltage begins charging a time delay network made up ofresistor R33 and capacitor C9. A comparator transistor, Q14, is drivenvia resistor R35 once the timing circuit output voltage reaches athreshold level. This level is determined by the voltage at the junctionof voltage divider resistors R34 and R37 (sourced by the initial sensevoltage), in addition to the base-emitter junction voltage of transistorQ14.

The operation of transistor Q14 results in simultaneous application ofbase drive for transistors Q10 and Q11, via respective base currentlimiting resistors R26 and R28. Transistor Q11, referenced to the sensevoltage, proceeds to drive transistor Q15 via resistor R36. Operation oftransistor Q15 reduces the comparative threshold voltage by loweringtransistor Q14 emitter potential. This positive feedback process isregenerative to speed up the switching action. The application of theiliac gate drive current is via output transistor Q10 and currentlimiting resistor R41. Resistors R27 and R38 are required to preventpossible adverse effects from leakage and transistors Q10, Q11 and Q15.

The operation of the circuit for the negative mains half cycle is thesame as described above, using the mirrored set of components.

During IGBT over-current conditions, sufficient voltage is developedacross current sense resistor R40 to bias on transistor Q18. This inturn provides base current drive for upward transistor Q10, immediatelyoperating the triac, to divert current away from the IGBT circuit.Resistor R39 limits transistor Q18 base current drive to a safe levelunder these conditions. This provides an inbuilt circuit protectionmechanism.

At dimmer over-voltage currents, the triac gate is directly driven byseries connector tranzorbs BZ1 and BZ2. Capacitor C10 is placed acrossthe triac gate-MT1 terminals in order to enhance the triac immunity todv/dt triggering from mains transients.

Inductor L1 limits the rate of transfer of load current from the IGBTcircuit to the triac on order to control line conducted EMI emissionlevels. The amount of inductance required for this function is relatedto the difference between the triac on-state voltage and the voltageacross the IGBT circuit current above just prior to triac operation. Thepresence of current sense resistor R32 in the IGBT circuit current pathintroduces additional voltage differential, there by influencing theamount of inductance required. An additional means of controlling lineconducted EMI emission levels is via shunt capacitor C11 which works inconjunction with L1 to fowl a second order low-pass-filter.

A particular advantage of the present circuit is the ability of thetriac control circuit (whether it would be voltage driven or currentdriven) to be controlled directly by the IGBT circuit rather than via athird centralised control block as in prior systems.

In the case of the voltage driven drive circuit, this essentiallymonitors the diode bridge voltage, under control of the operational IGBTin order to determine when triac firing should occur. The necessarycharge required for triac gate drive is accumulated from the availablemains voltage in the period of the half-cycle before commencement ofIGBT conduction. The triac is essentially fired when the diode bridgevoltage is reduced below a minimum set threshold. This minimum setthreshold is determined by zener diodes DZ2 and DZ3 which in the presentexample, said a minimum threshold of 20 volts (for the positive andnegative cycles). The voltage at the diode bridge is sensed bytransistor Q6 and resistor network R17, R16, R18 and R19 as would beunderstood by the person skilled in the art. The minimum voltagethreshold is determined by the components used (in this case the zenerdiodes DZ2 and, DZ3) and is generally set to exceed by a suitable marginthe conduction voltage for the IGBT circuit.

In the case of the current driven drive circuit, this essentiallymonitors the diode bridge current under control of the operational IGBT,in order to determine when triac firing should occur. The necessarycurrent required for triac gate drive is derived from the load currentresulting at IGBT conduction in the half cycle. Again, the triac isfired when the diode bridge current rises above a minimum thresholdwhich in this case, is set by resistor R32.

In this way, the circuit configuration is far simpler than prior artdesigns which require a separate centralised control block monitoringelectrical parameters of the IGBT circuit, determining when the triacshould be fired in relation to those sensed parameters and providingcontrol signals to the triac control circuit. Alternatively, thecentralised control block sometimes provides control signals to both theIGBT and triac control circuits independently of each other, based onpre-set tinting parameters.

A simplified block diagram of this circuit arrangement is shown in FIG.4, in which element 10 represents the first control circuit (IGBTcontrol), element 20 represents a first switch (IGBT), element 30represents the rectifying circuit (eg. Diode bridge), and element 40represents the second control circuit (triac control), which obtains itscontrol signals from first control circuit 10, via rectifying circuit30. Element 50 represents the second switch (triac), which is controlledby second control circuit, and element 60 represents the load.

In practice, the voltage driven triac driven control circuit ispreferred over the current driven triac drive circuit. However, each hasadvantages and disadvantages. The voltage driven triac drive circuitallows minimal size of FMC filter components which results in highestoverall product efficiency. The voltage driven circuit however requiresvoltage dropping elements to derive a power source from the mains,therefore introducing local power dissipation problems (only at lowconduction angle settings, where total overall dissipation is low).Further more, additional components are required to disable the triacdrive when no IGBT drive is present to achieve off-state conditions(only required for applications without series manually-operatedswitch).

In contrast, the current driven circuit does not require a power sourceconnection to the mains, and therefore no local power dissipation issuesare encountered. Further more, the lilac drive is one hundred percentdisabled when there is no IGBT drive to achieve the of state (this is anadvantage only for application without a series manually-operatedswitch). The current drive circuit however suffers from the disadvantagethat the presents of current sense components necessitates larger EMCfilter components, and lower overall efficiency is achievable.

Another circuit block provides circuit protection from over currentconditions which may arise from IGBT operation. During such conditions,sufficient voltage is developed across current sense resistor R42 tobias on transistor Q14. This in turn provides base current drive foroutput transistor Q1, immediately operating the triac, to divert currentaway from the IGBT circuit on the DC side of the diode bridge. ResistorR40 limits transistor Q14 base current drive to a safe level under theseconditions.

At dimmer over-voltage occurrences the triac gate is directly driven viaseries connected tranzorbs D1 and D2 and current limiting resistor R20.Capacitor C11 is placed across the triac gate MT1 terminals in order toenhance the triac immunity to dv/dt triggering from mains transients.

In this dimmer design topology, it is not necessary to incorporate aninductor to achieve the required RF emission level limits. A relativelysmall inductor may however by required to provide some degree of di/dtprotection for the triac during IGBT over current conditions. In normaloperation, the voltage appearing across the triac just prior to firingis of the order of a few volts, depending on the actual load currentmagnitude. This voltage is a function of the IGBT saturation voltage anddiode bridge forward voltage characteristics. At such low operatingvoltage levels, the triac switching action is more gradual than instandard high voltage triac applications. This results in an inherentsmooth transfer of current from IGBT to the triac, with low associatedRF emission levels. The addition of the inductor L1 however, slightlyincreases the RF emission component associated with transfer of currentfrom the IGBT to the triac. This corresponds to the small introducedcurrent wave form discontinuity at the point when the IGBT current dropsto zero.

Additionally, at the end of each mains half cycle where the triacnaturally commutates off, a burst of RF emission occurs, due to thediscontinuity in the load current wave form. Attenuation of thisemission is achieved by a capacitor C15 place across the dimmerterminals. An important additional role of this capacitor is inimproving the entire dimmer circuit immunity to EFT.

Another circuit block is an inductive load imbalance detector. Thefunction of the circuit block is to shut down dimmer control in the caseof excessively asymmetrical operation, which may be the result ofconnection to an unloaded iron-core LV lighting transformer. Dimmingoperation is suspended if the average voltage across the dimmerterminals for the positive and negative half cycles are not similar.

Alternatively, the dimmer circuit is caused to reduce its conductionangle until a DC component is reduced to below a threshold causing theonset of the DC component itself. Although possible, this technique isnot preferred as it would typically result in oscillation betweensymmetric and no asymmetric conditions.

Referring back to FIG. 1, two resistor divider chains made up ofresistors R43, R44, R29 and R45, R46 and R30 are used to sense the mainsvoltages appearing at the active and load terminals respectively. Whenreferenced to the bridge common (negative) terminal, these voltagesrepresent opposite polarities of the mains voltage across the dimmer.The divider junction of each chain is connected to opposite sides ofcapacitor C12, to produce a differential voltage proportional to thedifference in half cycle voltages. Two transistors, Q9 and Q10 are usedto produce a common-referenced signal if the differential voltageexceeds a threshold of approximately 0.6 volts. A latch circuit made upof transistors Q11 and Q20 and resistors R32 and R34 has input driven bythe imbalance detector output. A transistor Q21, wired as a low leakagediode, directs latch output from transistor Q11 collector to “sync”, ie.to drive the timing control bypass transistor Q12.

Transistor Q21 acts as a blocking diode to prevent any latch operationby the zero crossing detector. Base-emitter bypass resistors R31 and R33are required to minimise leakage in the respective transistors.Similarly, capacitors C5 and C16 are present to enhance EFT immunity ofthe latch circuit. In addition, capacitor C5 provides rejection for anyhigh frequency signal component from the imbalanced detector output.

When operating inductive loads, the dimer circuit incorporates amoderately sensitive triac assist in achieving an acceptable level ofperformance, particularly in terms of operating symmetry with worst caseload types, ie. low value VA, highly inductive loads such as exhaust fanmotors.

In normal dimming operation, the IGBT initially operates followed byfiring of the triac after a fixed time delay. During this pre-triacconduction delay time period, the inductive load current has anopportunity to develop in magnitude. This delay time therefore alsoincreases the ability of the triac to operate successfully with suchdifficult loads.

At very low conduction angle settings however, there may be insufficientload current available for reliable triac latching. In this case, a lowlevel load DC component will be sustained by the dimmer in combinationwith the non-linear load inductance. Under these conditions, there is nodanger of damage to the load due to the relatively low rms currentmagnitude. If load DC component levels become excessive operation of theimbalance detector will automatically shut down the dimmer control.

In general, capacitive input electronic LV transformers are notgenerally suitable for leading edge phase control dimmers owing to theadditional resulting dimmer power dissipation. The high capacitorcharging current pulses increase line conducted EMC emission levels andmay produce repetitive high frequency ringing bursts on the mainsvoltage waveform.

The dimmer circuit of FIG. 1 incorporates load-over current sensingapplicable during the IGBT conduction period. Dimmer connection to suchcapacitive loads result in sustained operation of the over-currentmechanism, producing even higher EMC emission levels. In addition, thehigh frequency and amplitude ringing current waveform which typicallypresent for the first few hundred micro seconds may result incommutation of the triac. If this condition prevails, the imbalancedprotector may cause the dimmer control to shut down. For electronictransformers with maximum rated load connected, this condition is farless likely to occur.

An alternative circuit configuration for the inductive load imbalancedetector of FIG. 1 as described above is now described with reference toFIG. 5, which shows an alternative circuit arrangement for the IGBTcontrol of FIG. 1.

The general operation of the imbalance detection process is described asfollows. A capacitor, used to represent conduction time, is repetitivelycharged from zero to a level determined by the prevailing half cycleconduction period. The voltage developed on this “conduction timedetection” capacitor is used to set the peak voltage on a secondcapacitor, to represent peak conduction time. This “peak conductiontime” capacitor is simultaneously discharged with a constant dc currentsink. The resulting “peak conduction time” capacitor voltage waveformcomprises two components. (1) A de component exists with magnitudeproportional to half cycle conduction period. (2) An AC component existsin, the form of a sawtooth, with magnitude determined by fixedparameters ie. capacitor value, magnitude of dc current sink andrepetition frequency (2× mains freq.).

If sufficient difference in alternate polarity half cycle conductionperiods exist, the resulting AC voltage waveform associated with the“peak conduction time” capacitor has double the normal amplitude, atonly half the repetition frequency (mains freq.). A simple amplitudethreshold detector, with dc blocking properties, is used to activate alatching circuit in order to disable dimmer operation when the conditionis detected as a steady state.

A more detailed description with reference to actual components involvedfollows: During load conduction period of dimming cycle, transistor Q2collector can source current via limiting resistor R203 to “conductiontime detection” capacitor C201. When dimmer reverts to thenon-conducting state, at the end of each half cycle, diode D200 isolatesany current associated with charging of main timing capacitor C7.

Transistor Q200 is used to reset C201 to zero volts at the start of eachhalf cycle conduction period. Associated pulsed base drive for Q200 isprovided by capacitor C200 in series with resistor R201. Diode D201 inconjunction with resistor R200 provides the necessary discharge path forC200 in preparation for next mains half cycle event. Resistor R202bypasses base-emitter of Q200 to reduce device off-state leakage, duringcharging period of C201.

Transistor Q201 is configured as an emitter follower, so that thevoltage across capacitor C202 must follow the peak voltage of C201,during brief period where Q201 base-emitter input is forward biased.Transistor Q202 in conjunction with bias resistors R204, R205 & R206 isconfigured as a current sink for C202.

The sawtooth voltage waveform across C202 is AC coupled to the base of“threshold detection” transistor Q203 via diodes D202/D203 and capacitorC203. Series connected diode D203 functions to provide enough signalvoltage drop so that Q203 is not driven under symmetrical dimmeroperating conditions, where input signal amplitude is normally low.Resistor R207 reduces Q203 device off-state leakage; in addition toproviding a reverse charge path for C203. Diode D202 also forms part ofthe reverse charge path for C203.

Under asymmetric dimmer operating conditions, Q203 is operated in pulsemode, at a low duty cycle. An RC network comprising R208 and C204 isused to provide an averaging function for the resulting pulse train.Transistor Q204 forms part of a latch circuit, which is triggered whenthe voltage across C204 reaches a critical level as defined by voltagedivider resistors R209 & R210 in conjunction with Q204 base-emitterthreshold potential. Transistor Q205 in conjunction with resistorsR211&R212 forms the remaining part of the latching circuit.

At mains power-up or at initial activation of PWM dimmer control drive,it is necessary to ensure that the latching circuit is cleared to theunlatched state for a number of complete mains cycles. This function isperformed by RC network comprising R213 and C205, which initially holdsthe base drive voltage for Q205 at a, level less than the emitterreference level.

It will be appreciated that the above has been described with referenceto a preferred embodiment and that many variations and modifications arepossible as would be understood by the parson skilled in the art

1-9. (canceled)
 10. A protection circuit in a phase control dimmercircuit that, in use, controls an inductive load, the phase controldimmer circuit comprising a first switch and a second switch, the firstswitch in use determining a firing angle for the second switch, and thesecond switch, in series with the inductive load, effecting conductionof the inductive load in response to the first switch, the protectioncircuit comprising: an imbalance detector for detecting an asymmetricaloperation in the inductive load by detecting a difference between aconduction period of consecutive positive and negative half cycles andregistering a load imbalance if the difference between the consecutivepositive and negative half cycles exceeds a preset threshold; circuitcontrol means for protecting the phase control dimmer circuit by causingthe phase control dimmer circuit to reduce a DC component in theinductive load upon detection of the asymmetrical operation, bycontrolling the first switch.
 11. A load imbalance detector in a phasecontrol dimmer circuit that, in use, controls an inductive load, thephase control dimmer circuit comprising a first switch and a secondswitch, the first switch in use determining a firing angle of the secondswitch, and the second switch, in series with the inductive load,effecting conduction of the inductive load in response to the firstswitch, the load imbalance detector comprising: a load DC componentdetector to detect a DC component in the inductive load by detecting aDC component across the phase control dimmer circuit; a comparator forcomparing a magnitude of the DC component detected by the load DCcomponent detector with a reference voltage; and a signal generatingmeans for protecting the dimmer circuit by generating a circuitshut-down signal if the DC component exceeds a pre-set DC voltagethreshold above the reference voltage.
 12. A load imbalance detector asclaimed in claim 11 wherein said load DC component detector detects a DCsub-component in a positive cycle and detects a DC sub-component in anegative cycle and wherein said magnitude of the DC component is thedifference between the respective DC sub-components.
 13. A loadimbalance detector as claimed in claim 12 wherein said load DC componentdetector includes a first resistor divider chain for detecting said DCsub-component in the positive cycle, and a second resistor divider chainfor detecting said DC sub-component in a negative cycle and wherein adivider junction of the first chain is connected to a first side of acapacitor and a divider junction of the second chain is connected to asecond side of the capacitor, a voltage across which provides saidmagnitude of the DC component.
 14. A load imbalance detector as claimedin claim 13 wherein said comparator includes a first pnp transistorhaving its base connected to said first side of said capacitor and itsemitter connected to said second side of said capacitor, and a secondpnp transistor having its base connected to said second side of saidcapacitor and its emitter connected to said first side of saidcapacitor, and each respective collector connected to an input of saidsignal generating means.
 15. A protection circuit as claimed in claim 10wherein the circuit control means causes the dimmer circuit to shutdown.
 16. A protection circuit as claimed in claim 10 wherein thecircuit control means causes the dimmer circuit to reduce a conductionangle of the dimmer circuit to a point where the DC component reduces tobelow a preset threshold.
 17. A phase control dimmer circuit comprisinga protection circuit that, in use, controls an inductive load, the phasecontrol dimmer circuit comprising a first switch and a second switch,the first switch in use determining a firing angle for the secondswitch, and the second switch, in series with the inductive load,effecting conduction of the inductive load in response to the firstswitch, the protection circuit comprising: an imbalance detector fordetecting an asymmetrical operation in the inductive load by detecting adifference between a conduction period of consecutive positive andnegative half cycles and registering a load imbalance if the differencebetween the consecutive positive and negative half cycles exceeds apreset threshold; circuit control means for protecting the phase controldimmer circuit by causing the phase control dimmer circuit to reduce aDC component in the inductive load upon detection of the asymmetricaloperation, by controlling the first switch.
 18. The phase control dimmercircuit as claimed in claim 17, wherein the circuit control means causesthe dimmer circuit to shut down.
 19. The phase control dimmer circuit asclaimed in claim 17 wherein the circuit control means causes the dimmercircuit to reduce a conduction angle of the dimmer circuit to a pointwhere the DC component reduces to below a preset threshold.
 20. A phasecontrol dimmer circuit comprising a load imbalance detector that, inuse, controls an inductive load, the phase control dimmer circuitcomprising a first switch and a second switch, the first switch in usedetermining a firing angle of the second switch, and the second switch,in series with the inductive load, effecting conduction of the inductiveload in response to the first switch, the load imbalance detectorcomprising: a load DC component detector to detect a DC component in theinductive load by detecting a DC component across the phase controldimmer circuit; a comparator for comparing a magnitude of the DCcomponent detected by the load DC component detector with a referencevoltage; and a signal generating means for protecting the dimmer circuitby generating a circuit shut-down signal if the DC component exceeds apre-set DC voltage threshold above the reference voltage.
 21. The phasecontrol dimmer circuit as claimed in claim 20 wherein said load DCcomponent detector detects a DC sub-component in a positive cycle anddetects a DC sub-component in a negative cycle and wherein saidmagnitude of the DC component is the difference between the respectiveDC sub-components.
 22. The phase control dimmer circuit as claimed inclaim 21 wherein said load DC component detector includes a firstresistor divider chain for detecting said DC sub-component in thepositive cycle, and a second resistor divider chain for detecting saidDC sub-component in a negative cycle and wherein a divider junction ofthe first chain is connected to a first side of a capacitor and adivider junction of the second chain is connected to a second side ofthe capacitor, a voltage across which provides said magnitude of the DCcomponent.
 23. The phase control dimmer circuit as claimed in claim 22wherein said comparator includes a first pnp transistor having its baseconnected to said first side of said capacitor and its emitter connectedto said second side of said capacitor, and a second pnp transistorhaving its base connected to said second side of said capacitor and itsemitter connected to said first side of said capacitor, and eachrespective collector connected to an input of said signal generatingmeans.